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Integrated Circuit and Syst...

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers

Svensson, Lars

Springer Berlin Heidelberg 2009

This book constitutes the thoroughly refereed post-conference proceedings of 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008, featuring Integrated Circuit and System Design, held in Lisbon, Portugal during September 10-12, 2008. The 31 revised full papers and 10 revised poster papers presented together with 3 invited talks and 4 papers from a special session on reconfigurable architectures were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-leakage and subthreshold circuits, low-power methods and models, arithmetic and memories, variability and statistical timing, synchronization and interconnect, power supplies and switching noise, low-power circuits; reconfigurable architectures, circuits and methods, power and delay modeling, as well as power optimizations addressing reconfigurable architectures

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Computer science Memory management (Computer science) Logic design Computer system performance Systems engineering Computer Science Logic Design Processor Architectures System Performance and Evaluation Arithmetic and Logic Structures Memory Structures Circuits and Systems

Monografía

monografia Rebiun09179867 https://catalogo.rebiun.org/rebiun/record/Rebiun09179867 100301s2009 gw | s |||| 0|eng d 9783540959489 978-3-540-95948-9 9783540959472 ed. impresa) UPNA0455687 UIB 314796888 UMO 87152 UMA.RE Svensson, Lars Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Recurso electrónico] 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers edited by Lars Svensson, Jos Monteiro Servicio en línea Berlin, Heidelberg Springer Berlin Heidelberg 2009 Berlin, Heidelberg Berlin, Heidelberg Springer Berlin Heidelberg digital Lecture Notes in Computer Science 0302-9743 5349 Acceso restringido a miembros del Consorcio de Bibliotecas Universitarias de Andalucía This book constitutes the thoroughly refereed post-conference proceedings of 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008, featuring Integrated Circuit and System Design, held in Lisbon, Portugal during September 10-12, 2008. The 31 revised full papers and 10 revised poster papers presented together with 3 invited talks and 4 papers from a special session on reconfigurable architectures were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-leakage and subthreshold circuits, low-power methods and models, arithmetic and memories, variability and statistical timing, synchronization and interconnect, power supplies and switching noise, low-power circuits; reconfigurable architectures, circuits and methods, power and delay modeling, as well as power optimizations addressing reconfigurable architectures Modo de acceso: World Wide Web Springer (CS) Computer science Memory management (Computer science) Logic design Computer system performance Systems engineering Computer Science Logic Design Processor Architectures System Performance and Evaluation Arithmetic and Logic Structures Memory Structures Circuits and Systems Monteiro, Jos SpringerLink (Online service) Lecture notes in computer science (Servicio en línea) SpringerLink eBooks (Servicio en línea) Springer eBooks Springer eBooks

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monografia Rebiun09179867 https://catalogo.rebiun.org/rebiun/record/Rebiun09179867 100301s2009 gw | s |||| 0|eng d 9783540959489 978-3-540-95948-9 9783540959472 ed. impresa) UPNA0455687 UIB 314796888 UMO 87152 UMA.RE Svensson, Lars Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Recurso electrónico] 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers edited by Lars Svensson, Jos Monteiro Servicio en línea Berlin, Heidelberg Springer Berlin Heidelberg 2009 Berlin, Heidelberg Berlin, Heidelberg Springer Berlin Heidelberg digital Lecture Notes in Computer Science 0302-9743 5349 Acceso restringido a miembros del Consorcio de Bibliotecas Universitarias de Andalucía This book constitutes the thoroughly refereed post-conference proceedings of 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008, featuring Integrated Circuit and System Design, held in Lisbon, Portugal during September 10-12, 2008. The 31 revised full papers and 10 revised poster papers presented together with 3 invited talks and 4 papers from a special session on reconfigurable architectures were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-leakage and subthreshold circuits, low-power methods and models, arithmetic and memories, variability and statistical timing, synchronization and interconnect, power supplies and switching noise, low-power circuits; reconfigurable architectures, circuits and methods, power and delay modeling, as well as power optimizations addressing reconfigurable architectures Modo de acceso: World Wide Web Springer (CS) Computer science Memory management (Computer science) Logic design Computer system performance Systems engineering Computer Science Logic Design Processor Architectures System Performance and Evaluation Arithmetic and Logic Structures Memory Structures Circuits and Systems Monteiro, Jos SpringerLink (Online service) Lecture notes in computer science (Servicio en línea) SpringerLink eBooks (Servicio en línea) Springer eBooks Springer eBooks