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Pipelined ADC Design and En...
Pipelined ADCs have seen phenomenal improvements in performance over the last few years. As such, when designing a pipelined ADC a clear understanding of the design tradeoffs, and state of the art techniques is required to implement today's high performance low power ADCs. Written for both researchers and professionals, Pipelined ADC Design and Enhancement Techniques provides: i.) A tutorial discussion, for those new to pipelined ADCs, of the basic design and tradeoffs involved in designing a pipelined ADC ii.) A detailed discussion of four novel silicon tested pipelined ADC topologies geared towards those looking to gain insight into state-of-the-art design in the area. The ADCs detailed include: - An 11-bit 45MS/s ADC which rapidly digitally calibrates in the background both DAC and gain errors - A 10-bit ADC with power scalable between 50MS/s (35mW) to 1kS/s (15µW) - A 10-bit ADC for use in sub-sampled systems with a technique to eliminate the front-end sample-and-hold - A 10-bit, 50MS/s ADC which uses a capacitive charge pump based approach to enable a very small power consumption of 9.9mW
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monografia Rebiun12343776 https://catalogo.rebiun.org/rebiun/record/Rebiun12343776 cr nn 008mamaa 110414s2010 ne | s |||| 0|eng d 9789048186525 978-90-481-8652-5 10.1007/978-90-481-8652-5 doi UPNA0269350 UPVA 996879774803706 UAM 991007780695804211 UCAR 991007923116504213 CBUC 991004878993606711 CBUC 991010403395606709 UR0325715 UMO 111927 UPCT u359537 TJFC bicssc TEC008010 bisacsh 621.3815 23 Ahmed, Imran Pipelined ADC Design and Enhancement Techniques Recurso electrónico-En línea] by Imran Ahmed Dordrecht Springer Netherlands 2010 Dordrecht Dordrecht Springer Netherlands XXV, 200p. digital XXV, 200p. Analog Circuits and Signal Processing Engineering (Springer-11647) Chapter 1: Introduction -- SECTION I: PIPELINED ADC DESIGN. Chapter Accesible sólo para usuarios de la UPV Recurso a texto completo Pipelined ADCs have seen phenomenal improvements in performance over the last few years. As such, when designing a pipelined ADC a clear understanding of the design tradeoffs, and state of the art techniques is required to implement today's high performance low power ADCs. Written for both researchers and professionals, Pipelined ADC Design and Enhancement Techniques provides: i.) A tutorial discussion, for those new to pipelined ADCs, of the basic design and tradeoffs involved in designing a pipelined ADC ii.) A detailed discussion of four novel silicon tested pipelined ADC topologies geared towards those looking to gain insight into state-of-the-art design in the area. The ADCs detailed include: - An 11-bit 45MS/s ADC which rapidly digitally calibrates in the background both DAC and gain errors - A 10-bit ADC with power scalable between 50MS/s (35mW) to 1kS/s (15µW) - A 10-bit ADC for use in sub-sampled systems with a technique to eliminate the front-end sample-and-hold - A 10-bit, 50MS/s ADC which uses a capacitive charge pump based approach to enable a very small power consumption of 9.9mW Reproducción electrónica Forma de acceso: Web Engineering Computer science Systems engineering Engineering Circuits and Systems Processor Architectures SpringerLink (Servicio en línea) Springer eBooks Springer eBooks Printed edition 9789048186518 Analog Circuits and Signal Processing