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Offset Reduction Techniques...
Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed. Since the offset voltages of the constituting sub-blocks of these converters (pre-amplifiers, folding circuits and latched comparators) present the definitive linearity limitation, the offset is the fundamental design parameter in high-speed CMOS ADCs. Consequently, offset reduction techniques must be employed, in order to achieve high frequency operation with low power and layout area. Averaging and offset sampling are the most widely used, both being thoroughly characterized: the most exhaustive study ever performed about averaging in both pre-amplifier and folding stages is presented, covering the DC and transient responses, all mismatch sources, termination, and a fully automated design procedure; existing offset sampling methods are carefully reviewed, and two new techniques are disclosed that, combined, yield a (nearly) offset free comparator. Other relevant topics include kickback noise elimination in comparators, reference buffer design, a technique to compensate (certain) IR drops, details on the layout and floorplan of cascaded folding stages, and an improved scheme to select reference voltages in fine ADCs of two-step subranging converters. Special emphasis is given to the methods of guaranteeing specifications across process, temperature and supply voltage corners
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monografia Rebiun11966099 https://catalogo.rebiun.org/rebiun/record/Rebiun11966099 cr nn 008mamaa 100301s2009 ne | s |||| 0|eng d 9781402097164 978-1-4020-9716-4 10.1007/978-1-4020-9716-4 doi UPVA 996887950703706 UAM 991007781518404211 UCAR 991007922543204213 CBUC 991004878174806711 UMO 109929 TJFC bicssc TEC008010 bisacsh 621.3815 23 Figueiredo, Pedro M. Offset Reduction Techniques in Highspeed Analog-To-Digital Converters Recurso electrónico-En línea] Analysis, Design and Tradeoffs by Pedro M. Figueiredo, JoÃo C. Vital Dordrecht Springer Netherlands 2009 Dordrecht Dordrecht Springer Netherlands digital Analog Circuits and Signal Processing Series Engineering (Springer-11647) Accesible sólo para usuarios de la UPV Recurso a texto completo Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed. Since the offset voltages of the constituting sub-blocks of these converters (pre-amplifiers, folding circuits and latched comparators) present the definitive linearity limitation, the offset is the fundamental design parameter in high-speed CMOS ADCs. Consequently, offset reduction techniques must be employed, in order to achieve high frequency operation with low power and layout area. Averaging and offset sampling are the most widely used, both being thoroughly characterized: the most exhaustive study ever performed about averaging in both pre-amplifier and folding stages is presented, covering the DC and transient responses, all mismatch sources, termination, and a fully automated design procedure; existing offset sampling methods are carefully reviewed, and two new techniques are disclosed that, combined, yield a (nearly) offset free comparator. Other relevant topics include kickback noise elimination in comparators, reference buffer design, a technique to compensate (certain) IR drops, details on the layout and floorplan of cascaded folding stages, and an improved scheme to select reference voltages in fine ADCs of two-step subranging converters. Special emphasis is given to the methods of guaranteeing specifications across process, temperature and supply voltage corners Reproducción electrónica Forma de acceso: Web Engineering Data transmission systems Systems engineering Engineering Circuits and Systems Input/Output and Data Communications Vital, JoÃo C. SpringerLink (Servicio en línea) Springer eBooks Springer eBooks Printed edition 9781402097157 Analog Circuits and Signal Processing Series