Descripción del título
Full-Chip Nanometer Routing...
As Moore's Law continues unencumbered into the nanometer era, chips are reaching 1000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of physics-aware and manufacturing-aware routing. At 90 nm and below, there are so many signal-integrity issues that design teams cannot manually correct them all. At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture. In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability
Monografía
monografia Rebiun08246611 https://catalogo.rebiun.org/rebiun/record/Rebiun08246611 cr nn 008mamaa 100301s2007 ne | s |||| 0|eng d 9781402061950 978-1-4020-6195-0 10.1007/978-1-4020-6195-0 doi UPVA 996886110903706 UAM 991007697869204211 UCAR 991007933792504213 CBUC 991004878221106711 CBUC 991000725534106712 UMO 62453 UPCT u358300 TJFC bicssc TEC008010 bisacsh 621.3815 23 Ho, Tsung-Yi Full-Chip Nanometer Routing Techniques Recurso electrónico-En línea] by Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen Dordrecht Springer Netherlands 2007 Dordrecht Dordrecht Springer Netherlands digital Analog Circuits And Signal Processing Series Engineering (Springer-11647) Accesible sólo para usuarios de la UPV Recurso a texto completo As Moore's Law continues unencumbered into the nanometer era, chips are reaching 1000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of physics-aware and manufacturing-aware routing. At 90 nm and below, there are so many signal-integrity issues that design teams cannot manually correct them all. At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture. In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability Reproducción electrónica Forma de acceso: Web Engineering Computer aided design Systems engineering Nanotechnology Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Nanotechnology Chang, Yao-Wen Chen, Sao-Jie SpringerLink (Servicio en línea) Springer eBooks Springer eBooks Printed edition 9781402061943 Analog Circuits And Signal Processing Series