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CMOS Single Chip Fast Frequ...
Recently, wireless LAN standards have emerged in the market. Those standards operate in various frequency ranges. To reduce component count, it is of importance to design a multi-mode frequency synthesizer that serves all wireless LAN standards including 802.11a, 802.11b and 802.11g standards. With different specifications for those standards, designing integer-based phase-locked loop frequency synthesizers can not be achieved. Fractional-N frequency synthesizers offer the solution required for a common multi-mode local oscillator. Those fractional-N synthesizers are based on delta-sigma modulators which in combination with a divider yield the fractional division required for the desired frequency of interest. In CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications, the authors outline detailed design methodology for fast frequency hopping synthesizers for RF and wireless communications applications. Great emphasis on fractional-N delta-sigma based phase locked loops from specifications, system analysis and architecture planning to circuit design and silicon implementation. The book describes an efficient design and characterization methodology that has been developed to study loop trade-offs in both open and close loop modelling techniques. This is based on a simulation platform that incorporates both behavioral models and measured/simulated sub-blocks of the chosen frequency synthesizer. The platform predicts accurately the phase noise, spurious and switching performance of the final design. Therefore excellent phase noise and spurious performance can be achieved while meeting all the specified requirements. The design methodology reduces the need for silicon re-spin enabling circuit designers to directly meet cost, performance and schedule milestones. The developed knowledge and techniques have been used in the successful design and implementation of two high speed multi-mode fractional-N frequency synthesizers for the IEEE 801.11a/b/g standards. Both synthesizer designs are described in details
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monografia Rebiun05584834 https://catalogo.rebiun.org/rebiun/record/Rebiun05584834 cr nn 008mamaa 100301s2007 ne | s |||| 0|eng d 9781402059285 978-1-4020-5928-5 10.1007/978-1-4020-5928-5 doi UPVA 996883875703706 UAM 991007697846204211 UCAR 991007933809904213 CBUC 991000725380706712 CBUC 991004879773106711 UMO 57949 UPCT u358286 TJFN bicssc TEC024000 bisacsh TEC030000 bisacsh 621.3 23 Bourdi, Taoufik CMOS Single Chip Fast Frequency Hopping Synthesizers For Wireless Multi-Gigahertz Applications Recurso electrónico-En línea] Design Methodology, Analysis, and Implementation by Taoufik Bourdi, Izzet Kale Dordrecht Springer Netherlands 2007 Dordrecht Dordrecht Springer Netherlands XII, 208 p. digital XII, 208 p. Analog Circuits and Signal Processing Engineering (Springer-11647) Accesible sólo para usuarios de la UPV Recurso a texto completo Recently, wireless LAN standards have emerged in the market. Those standards operate in various frequency ranges. To reduce component count, it is of importance to design a multi-mode frequency synthesizer that serves all wireless LAN standards including 802.11a, 802.11b and 802.11g standards. With different specifications for those standards, designing integer-based phase-locked loop frequency synthesizers can not be achieved. Fractional-N frequency synthesizers offer the solution required for a common multi-mode local oscillator. Those fractional-N synthesizers are based on delta-sigma modulators which in combination with a divider yield the fractional division required for the desired frequency of interest. In CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications, the authors outline detailed design methodology for fast frequency hopping synthesizers for RF and wireless communications applications. Great emphasis on fractional-N delta-sigma based phase locked loops from specifications, system analysis and architecture planning to circuit design and silicon implementation. The book describes an efficient design and characterization methodology that has been developed to study loop trade-offs in both open and close loop modelling techniques. This is based on a simulation platform that incorporates both behavioral models and measured/simulated sub-blocks of the chosen frequency synthesizer. The platform predicts accurately the phase noise, spurious and switching performance of the final design. Therefore excellent phase noise and spurious performance can be achieved while meeting all the specified requirements. The design methodology reduces the need for silicon re-spin enabling circuit designers to directly meet cost, performance and schedule milestones. The developed knowledge and techniques have been used in the successful design and implementation of two high speed multi-mode fractional-N frequency synthesizers for the IEEE 801.11a/b/g standards. Both synthesizer designs are described in details Reproducción electrónica Forma de acceso: Web Engineering Microwaves Electronics Telecommunication Systems engineering Engineering Microwaves, RF and Optical Engineering Circuits and Systems Electronics and Microelectronics, Instrumentation Communications Engineering, Networks Kale, Izzet SpringerLink (Servicio en línea) Springer eBooks Springer eBooks Printed edition 9781402059278 Analog Circuits and Signal Processing