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Low-power high-speed ADCs f...
Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit>1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for>2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size
Monografía
monografia Rebiun25622694 https://catalogo.rebiun.org/rebiun/record/Rebiun25622694 m o d cr cn||||||||| 081117s2008 ne a ob 000 0 eng d 271820567 307965808 316865219 437234685 443684422 607316562 646756228 666931415 698464859 746946738 756438418 767199533 815676625 823114918 958840979 964889118 985030894 994721251 1005746000 1035713091 1058109903 1060686987 1069523918 1078872563 1105588043 1110904215 1148078585 9781402084508 1402084501 9048178851 9789048178858 9781402084492 1402084498 10.1007/978-1-4020-8450-8 doi AU@ 000043481651 AU@ 000048655469 DEBSZ 430674635 NLGGC 317126989 NZ1 13072455 978-1-4020-8449-2 Springer http://www.springerlink.com GW5XE eng pn GW5XE VPI COO OCLCQ N$T OSU CEF MND E7B UBC IDEBK EBLCP OCLCQ A7U OCLCQ OCLCF BEDGE OCLCQ OCLCO YDXCP DEBSZ OCLCO OCLCQ OCLCO OCLCQ VT2 OTZ OCLCQ ESU OCLCQ UAB MYUTM STF OCLCQ BEATB OCLCQ U3W AU@ OCLCQ WYU YOU CANPU OCLCQ AUD ZHM WURST OCLCQ TEC 008020 bisacsh TEC 008010 bisacsh 621.3815322 22 Cao, Zhiheng Low-power high-speed ADCs for nanometer CMOS integration Zhiheng Cao, Shouli Yan Dordrecht Springer Science + Business Media B.V 2008 Dordrecht Dordrecht Springer Science + Business Media B.V 1 online resource (xiii, 95 pages) illustrations 1 online resource (xiii, 95 pages) Text txt rdacontent computer c rdamedia online resource cr rdacarrier text file PDF rda Analog circuits and signal processing series 0893-3405 Includes bibliographical references (pages 91-93) A 52 mW 10 b 210 MS/s Two-Step ADC for Digital IF Receivers in 130 nm CMOS -- A 32 mW 1.25 GS/s 6 b 2 b/Step SAR ADC in 130 nm Digital CMOS -- A 0.4 ps-RMS-Jitter 1-3 GHz Clock Multiplier PLL Using Phase-Noise Preamplification -- Conclusions and Future Directions Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit>1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for>2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size English Analog-to-digital converters- Design and construction Metal oxide semiconductors, Complementary- Design and construction TECHNOLOGY & ENGINEERING- Electronics- Circuits- Integrated. TECHNOLOGY & ENGINEERING- Electronics- Circuits- General. Ingénierie. Analog-to-digital converters- Design and construction. Metal oxide semiconductors, Complementary- Design and construction. engineering circuits Engineering (General) Techniek (algemeen) Electronic books Yan, Shouli Print version Cao, Zhiheng. Low-power high-speed ADCs for nanometer CMOS Integration. [Dordrecht?] : Springer, 2008 9781402084492 (OCoLC)227025628 Analog circuits and signal processing series